Hardware Single Step for the 8085

As usual my current developments tend to wander towards all directions, as the ever expanding universe... Although I haven't really finished any of my other "side jobs", I want to further develop the mini85 into a real single board CP/M computer, but more on that later.
This week, I looked for a Hardware Single Stepping circuit for the 8085. Something that proves that "everything is on the internet" is not true (if you didn't already knew), at least until up to now.
The internet came up with nothing, so I had to resort to older methods... Books, applications notes, etc... First of it was the 8080 datasheet, on the description of the READY line it states "Can be used for single stepping the processor" but this sentence is strangely absent from the 8085 datasheet (a nice circuit with one wait state is drawn instead). Then I found something on a great book "Microcomputers and Microprocessors - The 8080, 8085 and Z-80 Programming, Interfacing, and Troubleshooting" by John Uffenbeck. There are caveats, about the same as others and my previous pseudo-DMA circuit for the 8085, doesn't allow the use of dynamic RAM hidden-refresh (end of M1). I've redrawn it with gschem.


It is not exactly what I want. I want a single lever switch with 3 positions RUN, HALT, SingleStep. I found this one on Digikey a nice C&K switch that "has the looks" of a 1980 Computer and could do the job. The problem is that I need to do some adaptation from the schematics above to a single switch with 3 positions, the main problem is halt the computer when the switch is off (centre position) and at the same time set the FF clock low... I might need some magic...

8-bit single board computers

Before I build my own single board computer, I wanted to do a study of past and "present" single board computers that "could" run CP/M, focusing in their features and capabilities. Since I like CP/M-80 and I already managed to build a few breadboard computers that could run CP/M from a floppy or memory, I thought could build something more permanent.
Most of the SBCs I've listed below are for the Z80, or derivatives.

1. SB180 (from Micromint, details published on byte Sep-Oct 85 designed by Steve Ciarcia) uses a HD64180 (or Zilog's Z180) with 2 DMA channels, 2 Serial, floppy interface using FDC9266 (for high density disks) (update, I've changed the picture and here there's even a SB180FX).
   
   
2. P112 uses a Z182 with 2 DMA channels, 2 full serial and a FDC37C665 for floppy interface, extra serial ports, parallel port and possible IDE drive (PC-style super IO, includes high density) (new version was being sold here, apparently there wasn't enough critical mass).
   
3. CPU280 uses Z280 with 4 DMA channels, 2 serial ports and a FDC37C65 does the floppy interface (also high density disks), although some details can be found on the internet I was unable to find schematics.
   
4. N8VEM (designed by Andrew Lynch) uses a vanilla Z80, serial port with 16C550, huge SRAM 512K (mostly used as a RAM-disk), big Flash Rom 1Mb with operating system (CP/M) included, ECB bus interface, Floppy interface is an external board (new design, several boards and developers here), RTC and parallel interface (i82C55) and it's all open hardware.
   
5. YASBEC also uses Z180 but the hardware details are much more elusive in the internet, the disk format suggests 3.5 inch HD drives.
   
6. PROF80 uses a Z80, has a floppy interface with the UPD765, high density data separator, bit-bang serial interface, on the webpage there are more details ans schematics of other boards (graphics terminal) and upgraded version with Z180 (with FDC37C68, RTC and other goodies) some more details here.

I think after that review, I can settle on what I want for my CP/M SBC with the 8085. A 3.5 inch floppy (HD), 765 Floppy interface, 8085AH-2 @ 10.24MHz (2% overclocked) a 8256AH, 128K SRAM and 32KB ROM (with a debugger, Forth or Basic and boot). On the optional is a second serial port, a parallel port, a SD Card interface and an expansion port. I think I can skip the RTC as CP/M 2.2 doesn't need it and it's optional for CP/M 3.0 .
Front panel inputs I'd like to have a RUN/HALT/SINGLE STEP switch on the front, a RESET push-button and an interrupt push-button (maybe RST7.5 or TRAP). As for indicators a RUN/WAIT/HALT (green/yellow/red) LED, a INTR/INTA (red/green) and a HOLD/HLDA (only if there's an expansion port).

Arduino interface to SD Card

Finally managed to interface to a SDcard to the Arduino. There are several "tutorials" and even libraries written for the Arduino, but my objective was not to use any Arduino library or specific feature (like the integrated SPI port), otherwise porting the code to the mini68k would be more difficult.

I started with this example (this other seems easier) and then started "removing stuff" in order to fit my purposes. I only need the basic initialize, read sectors and write sectors. In order to boot and run CP/M from an SDcard I don't even need to read/write more than a single sector as CP/M reads/writes only one sector, furthermore deblocking (breaking up a 512 byte sector into 128 byte CP/M sectors) is easily managed by most CP/M flavours (CP/M-80,CP/M-86,CP/M-68k, CP/M-Z8000).
I battled with some Arduino functions, I particular serial.print() functions. I'm suspicious that something doesn't quite add up, some of the lines of text that should be printed are skipped for no apparent reason. It could be by the fact that I directly access the port pins (DDRB and PORTB) but since I don't change the serial pins there shouldn't be a problem...
After several tries I managed to write and read a sector of the flash.

The hardware is at its simplest form, it is a basic resistive divisor by 2 for the card inputs CS, SDI and SCK, the SDO output from the card is connected directly to the Arduino input pin.
Pins CD and WP are also connected directly, the card detect(CD) and write protect(WP) switches use a weak pull up feature from the micro. A low voltage drop regulator provides 3.3V to the card.
I used the Sparkfun SDcard adaptor, but since the "freeday disappointment" I promissed never to buy from them until the EURO is >= 2x the US dollar (from that point on I would be stupid, not stubborn). The circuit used is the one of the first example above, except that I didn't bother to have the correct 3.3V input, I decided to go to 2.5V as it is easier to obtain (two equal resistors) and the input tolerance of the SDcard must accept it correctly. Usual (CMOS) input levels are at 60% (2.2V for High or 1) and 30% (for Low or zero) of Vcc (of the card).
Now I only need to port the code to the 68k...

Next Project Minimal CP/M 68k

The Solarlight project has been taking more than normal, but the truth is I haven't had much time lately...so I decided to announce my next project, revive a minimal CP/M-68k system and document the process. The main components are a MC68008 CPU, a MC68901 MPU, 512K of SRAM, 32k EPROM, and a IDE/ATA connector. The MPU (multi-peripheral unit) will serve as UART and probably as basic memory manager, the IDE interface will probably be based in GIDE or something similar. While I'm still working on the schematics, I've already built the base circuit from my hand written schematics... here's a picture.

The sources and documentation of the code are available in Gaby's site. This site used the sources to build a VAX version, so the sources appear not to have suffered from too much of "bit rot".
For cross compiling and debugging I'll try to use binutils/gcc/gdb in remote mode. I'll try to build the cross tools (elf format, coff has been since long time killed) and a remote gdb-stub to download and debug some initial code... we'll see how it goes..
Here I've already built the cross-compiler toolchain for m68k-elf (binutils-2.20, gcc-core-3.4.6, gdb-6.8 and newlib 1.18.0), I didn't use a more recent one because from searching gcc-3.x.x is easier to cross compile with the newlib, and I wanted to use a smaller libraries than libc.
Download the sources from the gnu ftp site (except for newlib that is here), I followed this guide because not only it appeared simpler (no "bootstrap compiler" step) but also it is dedicated to embedded systems. Don't forget to move newlib and libgloss inside the gcc directory and after the binutils compile put them in the path. I also used gnu gdb instead of insight but no other than that.
Finally set the path in your .profile for your convenience, see here for details on OpenSuse.
My first objective after building the system on a breadboard is to download a small m68k assembly program to the EPROM EMULATOR and see it run, then a small C program and finally a gdb-stub. Then I'll have to repeat the process since from that point on there must be a change in the linker file as programs stop being linked to ROM but linked to RAM.
I've successfully assembled a "loop:nop,nop,bra.s loop" but a few problems or "unknowns" remain...
I've created my simple assembly file called test.S

/*
* test.S -- test file for assembler output
*/

#include "asm.h"
.title "test.S - test file for assembler output m68k-elf-as"
#define STACKSIZE 0x4000

.data

.text

.extern __stack

.global SYM (_start)
SYM (_start):
nop
nop
bra.s _start

I assemble it with "m68k-elf-gcc -c test.S -o test.o" then link it still with gcc "m68k-elf-gcc test.o -o test.x -nostartfiles -nostdlib -v -fpic -WL,Ttest.ld"
I had to include the -nostartfiles and -nostdlib to remove the standard crt0 and the global constructors for C++.
My current linker file is very simple and probably some things are missing for a full C program compilation but for now things appear to be ok.

/* ld file for rom programs */
/* for 8 cycles rom is at 0x00000 (fetch SP and PC), from then on 0x80000
/* STARTUP(crt0.o) - no startup file*/
OUTPUT_ARCH(m68k)
OUTPUT_FORMAT(srec)
SEARCH_DIR(.)
/*
*Setup the memory map of mini68k, stack grows down from high memory.
*/
MEMORY {
ram (rwx) : ORIGIN = 0x01000, LENGTH = 0x80000-0x01000
rom : ORIGIN = 0x80000, LENGTH = 64K }
/*
* allocate the stack to be at the top of memory, since the stack
* grows down, also PUSH => -(SP) = xx, i.e. predecrement therefore
* first stack address never gets written
*/

PROVIDE (__stack = 0x80000);

SECTIONS
{
.text :
{
_stext = .;
*(.text .text.*)
. = ALIGN(0x4);
_etext = .;
} > rom

.data :
{
*(.data .data.*)
_edata = .;
} > ram

.bss :
{
. = ALIGN(0x4);
__bss_start = . ;
*(.bss .bss.*)
_end = ALIGN (0x8);
__end = _end;
} > ram
} /* missing in the initial file - causes an error ld does not complain! - beware */

Then I can also successfully convert the object file test.x to a SRECORD file with the command "m68k-elf-objcopy -O srec test.x test.S19" and then revert the intermediate object file test.x to assembler with "m68k-lef-objdump -d -X test.x > test.dis"
After successfully removing all the initialization code gcc attaches to your code (with -nostartfiles -nostdlib(p.s. you only need the first one since you don't add any library function)) I was left with one question, why is my code placed at absolute address 0x80000054?? when I told in the linker file to put it at 0x80000 (less a few zeros in the middle) Here is the disassembly:

test.x: file format elf32-m68k

Disassembly of section .text:

80000054 <_start>:
80000054: 4e71 nop
80000056: 4e71 nop
80000058: 60fa bras 80000054 <_start>

Ok, this was a bug. I forgot a } in the memory definitions of the linker file *.ld... After adding it the code was located at the correct place 0x80000.
Well there are still some hurdles to overcome, namely:
- placing the start SP and start address in vectors 0 and 1;
- place the other vector in ram
- place the code in proper ROM addresses (and the initial SP,PC)
- download the code and see it run...
... the path through cross-gcc appears to be hard ...

Mini85 has left the building...

I decided to dismantle the Mini85 circuit to gain some desktop area for the next year. It was the biggest and more complex breadboard project I've ever done. I did not manage to build it in three standard breadboards, but I still find it small enough. With a single PAL (maybe a 16V8) I'm pretty sure it could fit the three boards.
The next step is use what I've learned from this Mini85 project add it to the PCB design and USBKeyboard and build a eurocard (100x160mm) CP/M computer.
Here is his last picture in this format...Mini85 "will be back" soon... in PCB format...

Formating a floppy in Mini85

My list of softwear and hardware tasks is becomming shorter by the day. That is the number of new tasks added during the week is less than the tasks I finish during the weekend...
This weekend I finished the formating function and the display help function. On the hardware I changed the regulated power supply by a home build switching power supply, I've also changed the Motor on timer to 30 seconds to reduce wear on the floppies.
I've also created a task lisk on the blog's front page so it's easy to keep track of the TO DO list on the Mini85. I think it is a good idea, to keep a todo list for each project while it is running.I'll keep a list alive and maintained until a new project comes along, then I'll do a new one.
The format routine had a few details, the interrupt routine had to be changed to support the read/write operations and format operations.

Two pictures of the switching power supply, pretty standard. An LM2575-5.0 simple switcher, a RENCO 330uH inductor with IRMS 3 Amp capability (an old sample I had) and a schottky diode 1N5819 (here the diode is only capable of IRMS 1A)...

Using a CP/M Simulator

Since I started the project I started searching for CP/M simulators. In order to boot and use my system I needed a tool to build CP/M (assembling the CCP,BDOS,CBIOS and CBOOT), and transfering files to the disks. I found many that are a bit outdated here, and two great simulators with loads of cp/m software ready to run: Z80pack and SIMH/Altairz80 .

I setteld with Altair Z80 SIMH because it suited better my project. On the processor side allows you to change form the standard Z80 of most simulators to a 8080 processor, you can easily reduce the memory to 32Kb, it also has the boot disks and source (although in Z80 format) for CP/M 2.2, CP/M 3, and MP/M II. Finally and also very important, not only it supports the disk format I wanted to use (3.5 inch 1.44Mb, i.e. as used by P112) as also supports accessing the floppy disk directly.

As recommended here, I used a image file to transfer the files and then used NTRAWRITE to transfer the files to the floppy. I am using a USB 3.5 inch drive and the other usual tools to read and write CP/M disks didn't work as they used direct access to the UPD765 in regular PC.
The procedure is easy, start altairz80 and type in:

sim> set hdsk1 format=p112
sim> attach hdsk1 \\.\B:
sim> show hdsk1
HDSK1, 1474KB, attached to \\.\B:, P112, WRTENB, QUIET,
T:160/N:18/S:512
sim> go

At the moment I can only use CP/M 3 for reading and writing the disk images, because for CP/M 2.2 one needs to adapt the bios specifically for each hard disk.
When all the files have been transferred to the disk image, close the simulator and use NTrawrite to write the floppy image into the floppy.

8085 CP/M computer

It is amazing how the ideas flow once you put the schematic on paper... or screen... I wrote a list of possible improvements for the next circuit iteration.

Hardware:
- try (again) changing the FDC765 clock circuit down to 4MHz;
- change the FDC interrupt to RST7.5;
- change CRT_RXD input to RST6.5;
- change RDR input to RST5.5 (instead of SID);
- change PUN output to one of the 74HC259;
- do a system request input in INTR or TRAP inputs;
- do the LPT interface (with STROBE and PERROR);
- upgrade the system to full 64k bytes. (play Zork!)
- decide what to do with SID input and SOD outputs ?
- lights for RDY, INTA, floppy, etc..
- add the switching power supply and the MOTOR ON one-shot to the schematics.

Software:
- disable CRT/RDR interrupts while on FDC read/write cycle (blocks the system);
- put the processor in HALT while waiting for a character (save power);
- implement the RDR and PUN functions;
- implement the LST function;
- during a warm boot, read the operating system all at once instead of sector by sector (faster);
- change interrupts to follow the hardware changes above;
- either put most of the BIOS in ROM (32K) or in upper RAM (64K).

The problem with the 64K expansion is that it would use a second RAM IC, that takes up valuable breadboard space (as I have a three breadboard limit), plus probability of failing due to wiring. I think I can still make some more optimizations on the IC's used.

Mini85 - First Circuit Schematics

The first version of the schematics is finished... There are still some optimizations to do, specially regarding the logic gates. The resistors in the directly connected to the 8085 are not really necessary but handy if a later expansion is needed.
This part of the circuit also include the FDC-DMA blocking circuit, the IO decoding and the Memory decoding and the reset circuit.

The second sheet holds the Memory (ROM and RAM), the addressable latch for swapping RAM/ROM and a single Output bit for the serial port (CRT_TXD).

The third sheet holds the floppy disk interface, data separator FDC9216, write clock divider, Drive interface and floppy connector.

The forth sheet (still to come) will hold the switching power supply and the motor on circuit.
It is still difficult to print schematics with gschem, I tried the light output but it is not the best, I'll have to try again with light background and no colors. I will also try to print out a list of connections to do the wire wrapping circuit.

Finished the Hardware

I had one last hardware modification to try out, changing the clock of the disk system to 4MHz would save some power (due to the reduced clock), spare an inverter (buffer) and reduce the noise interference.
It turned out it could not be done, at least as far as I tried. The data separator FDC 9216 cannot read 500kbps without an 8MHz input, from the datasheet it is impossible to get that rate without an 8MHz clock. The WRCLK divisor could work but I would need to change the divisor ratio, but the 765 didn't seem to like the 4MHz clock at all as it was unable to read any sector, even increasing the byte loop and changing the specify parameters.
Finally I have a reached the final hardware configuration for this project. My current IC count is only 16!

• 8085AH-2 @ 4MHz (8MHz crystal)
• 74HC573 (address latch)
• 27C256 (EPROM emulator 32K bytes)
• 62256ALP-10 (system RAM 32K bytes)
• MAX232 (serial interface)
• 7400 (used as 4 inverters...!!)
• 74HC139 (address and IO decoder)
• 74LS08 (address decoder, only 2 ports used)
• 74HC259 (addressable latch, serial port, memory flip)
• LM555 (motor on delay)
• 74HC161 (WRCLK divider)
• UPD765 (Floppy Disc Controller IC)
• 74HC14 (FDC Interface to the drive)
• FDC9216 (Data separator for 3.5 HD drive)
• 74LS32 (FDC Interface to the drive)
• 74LS240 (FDC Interface to the drive)

There might be some more optimizing to do, I'm going to try and use gEDA gschem to draw the schematic and I'll post them as soon as their finished.

Mini85 first CP/M boot

It's alive! There is still a small bug, but I think I've found it already... The Warm Boot sequence (after a CTRL-C) fails. I'm probably not moving correctly the sectors from the disk buffer to the correct place in memory, since the cold boot routine (just after reset) is woring ok.
Next I need to clear this bug and try some CP/M software that runs in 24k since my system needs 8k for the operating system. Since I am using a "standard" CP/M format of a not-so-old CP/M system (P112), and this format is supported by CP/M 3 running in simulator SIMH (the version emulating the Altair), I can create disks and transfer files from the simulator to the real Mini85.
Update: I managed to write a Floppy with a copy of CP/M 2.2 startup disk used in SIMH, corrected the warm boot code, and I filmed the boot sequence with some daylight.
Here's the new video...

Creating a CP/M boot sector

In Andy Johnson-Laird's book "The Programmer's CP/M Handbook" the major steps of bringing up your own CP/M system are well explained and in this order:

1. Create your new BIOS with the appropriate device drivers in it. Assemble this so that it will execute at the top of memory (and determine the start address of the OS).
2. Create the new versions of the CCP and BDOS with all addresses inthe instructions changed so that they will be correctly located in memory just below the new BIOS. (Nowadays you can assemble this code instead of using MOVCPM)
3. Create or modify a CP/M bootstrap loader that will be loaded by the firmware that executes when you first switch on your computer.
4. Using Digital Research tools to bring the bootstrap loader, CCP, BDOS, and BIOS in the first tracks of the floppy. (I used my ROM monitor for this).

I skipped steps 1 and 2 because in a previous "incarnation" of the system I did it and I know it will be the not so dificult part. So I rewrote my Monitor disk read and write to be a little more "efficient" and used them in the bootstrap code.

After a RESET, the 8085 checks if there is a disk in drive. If so, seeks drive 0 (or A:) to track 0, and tries to read sector 1 (sector zero does not exist, only for historical reasons) into memory address 100H.

Then jumps to address 100H if it contains the byte value 0F3H, it is the code of a disable interrupts instruction (DI) in the 8080, 8085, z80, nsc800 family of microprocessors.

The bootstrap loader then reads the rest of operating system into memory (CCP,BDOS,BIOS) from the first track (sectors 2 and on). Then a jump is made to the cold boot function in the BIOS, then CP/M starts.

I used SIMH and CP/M 2.2 for assembling the code, I fell in a little trap with ASM. It recognizes the instructions SIM and RIM as labels not as instructions... I only found this by reading the assembler print out. I had to use a DB 30H for SIM and a DB 20H for RIM, then it worked ok.

The Boot Sector Code is posted here.

More pseudo-DMA circuits

In my search for new alternatives I found two more schematics in a very good article. The article titled "Floppy Disk Data transfer techniques" by T. Marshall and J. Attikiouzel and was published in IEEE Micro in December 1983. The article is a bit Z80 centric but easily adaptable to other microprocessors.

The first technique is using a edge triggered interrupt and the HALT instruction (NMI in the Z80 or RST7.5 or TRAP in the 8085), the interrupt routine is void but although in the z80 it is automatically cleared on interrupt entry, on the 8085 two extra instructions must be used in the ISR.

The second technique is the WS (wait state) insertion while waiting for the floppy to get the data. This is a similar technique to the one I'm using in the mini85, the schema proposed has more control options as sensing the interrupt call and determine an error, conditional enabling of WS insertion.

On the Z80 both these methods allow and profit in terms of timing by executing the INI instruction, one instruction fetch with 3 operations executed (IN (C),INC HL,DCR B).

Hopefully I will use a combination of both methods, WS insertion for data reads and writes and halting the processor for seek/recall operations.

The 8085, FDC 765 and Pseudo-DMA operation

My problems with the previous configuration began when my PC USB-Floppy drive stopped formating or recognizing my modified 3.5 DD disk. A problem that occurred frequently and inconveniently solved by removing the disk and inserting it again.
After reading about lots of complaints about small disk sizes I decided to go the extra mile and implement the said pseudo-dma circuit and routine for 3.5 HD drives. Yes, I had to ask some more questions in the yahoo group, but someone with infinite patience explained me the easy way to do it. Here is the schematic I used for pseudo-dma and the 8085 to read 3.5 HD floppies.

The operation of this circuit is the following, the read operation is started and a special IN instruction (addresses 2xH) lock the processor in a wait state and asserts DACK. When the byte is ready (this can last a full rotation of the disk) DRQ is asserted unlocking the processor and completing the read.

There is a problem with this schematic and my program, if an interrupt occurs during a normal read (signaling an error during the read) the processor is unlocked but the first byte read is already the result byte. Beeing RST6.5 level triggered, when the next instruction to the IN is fetched there is no longer a pending interrupt (765 INT line gets deasserted when the first byte of result phase is read) and the system hangs in execution phase.

One alternative would be to use RST7.5, it is latched by the processor, but on entry in the interrupt routine one should be aware that ACC could contain the first result phase byte. There is a special case where it could not be! As in an error occurs exactly after reading a byte.

The big issue is that a read or write during execution phase must be completed at 16us nominal (13-11us worst case) and testing if byte is ready or interrupt is pending takes time.

My next "development" will be polling interrupts for seek and recalibrate operations, as for the execution phase, maybe go back to the NO DMA mode (ND=1) and use HALT as a wait for interrupt instruction, do the test for results phase and read in the byte.

As for a latter hardware development would be to reduce the 765 clock from 8MHz to 4MHz and use CLKOUT instead of X2 buffered (save a gate).

3.5 inch drives and FDC 765

Before I started the mini85 project, I started gathering information on the floppy drives and CP/M interface. I came across this page. It made me aware of a few constraints on my project:
- it would be difficult to find a project with modern day 3.5 inch drives (later I found this one);
- they would not use MFM at 1MHz bit rate to achieve 1.44Mb densities because it is too fast for the processor (13us) and some sort of DMA would be necessary.
I was reading comp.os.cpm and a new yahoo group started for people that would want to build their own CP/M computer. My project was going that way so I joined in, draw up some schematics and started writing code and asking questions.
After initial hardware development and some code, I managed to read and write a 720k floppy on the mini85. To get the best processor speed and least overhead, the 8085 was running at 10.24MHz (2.5% over clocking) and a 8256AH-2 connected to the CLKOUT (@5.12MHz) for the serial interface.
Regarding the interface between the 8085 and the 765, I used no interrupts (although connected) and polled In/Out as the 8085 is perfectly capable of polling the 765's status and reading the data in less than 26us.
I was using a PC to read/write/format a normal HD disk with the hole closed with tape, and I was using DEBUG in MSDOS to write sector on the disk.
As for circuits I tested the one used in prof80 and the one used in the ZX Spectrum +3, in the end I settled for my version of the prof80, i.e. I changed the data separator to a FDC9216 and used a 8MHz clock to the FDC9216 and UPD765, an a 1MHz divider (74LS161) for the 765's WRCLK. I then compromised the 8085 clock to 8MHz so that with a simple change of clock input, either X2 on the 8085 or CLKOUT, I could use 720k or 1.44Mb floppies.

Back from Holidays

Back from Holidays, a wonderful week in Sardinia with sun, good food and fantastic sea.
I've tried doing a small schematic with gEDA but in the end I went for "Paintbrush", sorry if my skills are not "excellent". When I use linux I'll try to use Dia or a similar for later postings.

I've decided to use the SID and SOD lines for auxiliary input (RDR: - reader in CP/M 2.2) and auxiliary output (PUN: - punch in CP/M 2.2).

I used RST5.5 for direct serial input, the inverter (74LS04) is needed for generating a interrupt (5V) at the start bit (GND), then interrupts are temporarily disabled during reception. A timing loop waits for the middle of the start bit and checks if it is still low (i.e. the RST5.5 pin is at 5V as it is inverted), if not it was a false start bit and exits the interrupt service routine (ISR). From then on reception depends on a software timing loop, inversion of the sensed interrupt line, and shifting the bit in.
The received character is placed in a buffer and a buffer full flag byte is set. The code is posted below as a picture. I'm still not very "experienced" with blogging and placing code snippets online, so I made a "png" with yellow background, it looked better than any other alternative...

Mini85 - before holidays

Just before going for a week of holidays in Sardinia I thought it would be interesting to post a picture of Mini85 as it is now. The 3.5 inch drive and the connection to the board. I'm sliming the board as much as I can. I think it is possible to remove one IC or another and/or change one or two of the ICs by one with more or different functions. For now it boots CP/M.

I'm also trying to develop a AltairZ80 SiMH configuration that resembles the Mini85, I managed to have a 8080 system with 32k of RAM, but then I couldn't build the operating system. I'm also having some issues with the disk format, although I'm using P112 format it only works well in a cp/m 3 configuration.

Back to the mini85

Today I tried something different on the 8085, and with good results!!
My first attempt for a software serial port used SID and SOD line for Receive and Transmit signals and bit-bang the serial signals at 2400 baud 8-N-1.
Then I realized that one of the CP/M BDOS calls needed a different implementation. The functions DirectIO and Read Console Status needed the system to receive a char and keep it in a buffer, until the processor asks for it. Reception must be an asynchronous process!
I though about it and without changing much of the previous routine, I connected an interrupt line of the 8085 to an inverted receive line. First I tried the edge triggerd RST7.5 detecting the down flank of the start bit (but then using SID line to get the status and then RST6.5 to detect the start-bit and to read the input line. When an interrupt occurred the serial reception routine would receive the character, store it in a buffer and in a auxiliary memory position store a "buffer full" status. The CP/M function could then be correctly executed.
Instead of using 2 lines (SID and RST7.5), I used only one RST6.5, after the interrupt is received it is possible to "pool" the RST line with the RIM instruction! I save a input line and a few more instructions. It is now apparent to me that the AUX_IN and CONSOLE_IN can both be implemented by software and without using the SID line!
Removing the 8256 added some other problems, I needed a digital output pin to flip the ROM from 0000H to 8000H (and the RAM the other way), for this I added an addressable latch 74LS259.
Have a great weekend.

Minimalist CP/M system

The idea came up last year when I learned that the floppy was considered dead. I decided to go back in time and build the smallest and simplest CP/M computer that still used a floppy (90mm / 3.5 inch) as storage media.
My project objectives were the following:
- build a CP/M v2.2 compatible computer;
- use the smallest number of integrated circuits and the simplest possible configuration;
- no programmable logic devices, only 74' and 40' series;
- use a 3.5 inch floppy disk as storage;
- the console for the CP/M system would be a terminal VT100 (on a Laptop linux/windows);
- be able to build an fully functioning computer in a breadboard;
- if possible do most of the software development in linux;
- build a wire-wrap version of the final hardware;
- design a PCB, build a box to host it and build a computer.
I started searching computers I knew that supported CP/M, and based the design from it. I looked at the Amstrad CPC 664 and PCW series, and also at the Sinclair Zx Spectrum +3. All these came from effectively the same place so their floppy disk interface was very similar. The used a NEC UPD 765 and a data separator (FDC 9216 or SED 9240) for the MFM encoding.
For the processor I settled on a Intel 8085 (8085AH-2) because I had a few in my parts box, it had an on-chip oscillator and seemed simple enough to build the console serial interface with the SID and SOD lines. The extra address decoder 74573 seemed a cheap option compared to the clock generation circuit for the Z80. I also have a NSC800 but not so much hardware information on it. Using the 8085 at 8MHz also allowed me to drive the UPD765 at the same clock or 4MHz with little or no changes. I also had it running it at 10.24MHz, but then the floppy disk needed a separate oscillator.
For the memory I wanted to use my EPROM emulator bought on ebay and a small enough RAM to run CP/M. I chose a 62256 with 100ns access time and my emulator simulating a 27C256, so 32K RAM and 32K ROM.
As a help circuit, to get me started with a serial interface and some digital inputs and outputs I added an Intel 8256AH. This IC is not very easy to find but it packs two 8bit ports, a serial interface and some timers. The perfect peripheral IC, a bit like the 6522 VIA for the Motorola 6800 or Rockwell 6502 processors.
I'll post more on this one.