More pseudo-DMA circuits

In my search for new alternatives I found two more schematics in a very good article. The article titled "Floppy Disk Data transfer techniques" by T. Marshall and J. Attikiouzel and was published in IEEE Micro in December 1983. The article is a bit Z80 centric but easily adaptable to other microprocessors.

The first technique is using a edge triggered interrupt and the HALT instruction (NMI in the Z80 or RST7.5 or TRAP in the 8085), the interrupt routine is void but although in the z80 it is automatically cleared on interrupt entry, on the 8085 two extra instructions must be used in the ISR.

The second technique is the WS (wait state) insertion while waiting for the floppy to get the data. This is a similar technique to the one I'm using in the mini85, the schema proposed has more control options as sensing the interrupt call and determine an error, conditional enabling of WS insertion.

On the Z80 both these methods allow and profit in terms of timing by executing the INI instruction, one instruction fetch with 3 operations executed (IN (C),INC HL,DCR B).

Hopefully I will use a combination of both methods, WS insertion for data reads and writes and halting the processor for seek/recall operations.

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