8085 CP/M computer

It is amazing how the ideas flow once you put the schematic on paper... or screen... I wrote a list of possible improvements for the next circuit iteration.

Hardware:
- try (again) changing the FDC765 clock circuit down to 4MHz;
- change the FDC interrupt to RST7.5;
- change CRT_RXD input to RST6.5;
- change RDR input to RST5.5 (instead of SID);
- change PUN output to one of the 74HC259;
- do a system request input in INTR or TRAP inputs;
- do the LPT interface (with STROBE and PERROR);
- upgrade the system to full 64k bytes. (play Zork!)
- decide what to do with SID input and SOD outputs ?
- lights for RDY, INTA, floppy, etc..
- add the switching power supply and the MOTOR ON one-shot to the schematics.

Software:
- disable CRT/RDR interrupts while on FDC read/write cycle (blocks the system);
- put the processor in HALT while waiting for a character (save power);
- implement the RDR and PUN functions;
- implement the LST function;
- during a warm boot, read the operating system all at once instead of sector by sector (faster);
- change interrupts to follow the hardware changes above;
- either put most of the BIOS in ROM (32K) or in upper RAM (64K).

The problem with the 64K expansion is that it would use a second RAM IC, that takes up valuable breadboard space (as I have a three breadboard limit), plus probability of failing due to wiring. I think I can still make some more optimizations on the IC's used.

Adjusting the Rear Axel

From the title of the blog, I bet you would expect more bike postings... Here is the second one...
Two weeks ago, when starting the rear Axel moved. If the Axel is not securely fastened when you're really pushing the pedal, the Axel can shift forward (on the crank and chain side) and the wheel becomes bocked by the frame, like in the picture below.

Fixing it is quite straight forward, unscrew the axel, hold the wheel in the center while stretching the chain, and progressively securely fasten the Axel. A good guide on Bikes can be found here, although the author of said site prefers direct drive, my Kronan is a "Single speed" with a "Coaster Break".

Mini85 - First Circuit Schematics

The first version of the schematics is finished... There are still some optimizations to do, specially regarding the logic gates. The resistors in the directly connected to the 8085 are not really necessary but handy if a later expansion is needed.
This part of the circuit also include the FDC-DMA blocking circuit, the IO decoding and the Memory decoding and the reset circuit.

The second sheet holds the Memory (ROM and RAM), the addressable latch for swapping RAM/ROM and a single Output bit for the serial port (CRT_TXD).

The third sheet holds the floppy disk interface, data separator FDC9216, write clock divider, Drive interface and floppy connector.

The forth sheet (still to come) will hold the switching power supply and the motor on circuit.
It is still difficult to print schematics with gschem, I tried the light output but it is not the best, I'll have to try again with light background and no colors. I will also try to print out a list of connections to do the wire wrapping circuit.

Finished the Hardware

I had one last hardware modification to try out, changing the clock of the disk system to 4MHz would save some power (due to the reduced clock), spare an inverter (buffer) and reduce the noise interference.
It turned out it could not be done, at least as far as I tried. The data separator FDC 9216 cannot read 500kbps without an 8MHz input, from the datasheet it is impossible to get that rate without an 8MHz clock. The WRCLK divisor could work but I would need to change the divisor ratio, but the 765 didn't seem to like the 4MHz clock at all as it was unable to read any sector, even increasing the byte loop and changing the specify parameters.
Finally I have a reached the final hardware configuration for this project. My current IC count is only 16!

• 8085AH-2 @ 4MHz (8MHz crystal)
• 74HC573 (address latch)
• 27C256 (EPROM emulator 32K bytes)
• 62256ALP-10 (system RAM 32K bytes)
• MAX232 (serial interface)
• 7400 (used as 4 inverters...!!)
• 74HC139 (address and IO decoder)
• 74LS08 (address decoder, only 2 ports used)
• 74HC259 (addressable latch, serial port, memory flip)
• LM555 (motor on delay)
• 74HC161 (WRCLK divider)
• UPD765 (Floppy Disc Controller IC)
• 74HC14 (FDC Interface to the drive)
• FDC9216 (Data separator for 3.5 HD drive)
• 74LS32 (FDC Interface to the drive)
• 74LS240 (FDC Interface to the drive)

There might be some more optimizing to do, I'm going to try and use gEDA gschem to draw the schematic and I'll post them as soon as their finished.

Mini85 first CP/M boot

It's alive! There is still a small bug, but I think I've found it already... The Warm Boot sequence (after a CTRL-C) fails. I'm probably not moving correctly the sectors from the disk buffer to the correct place in memory, since the cold boot routine (just after reset) is woring ok.
Next I need to clear this bug and try some CP/M software that runs in 24k since my system needs 8k for the operating system. Since I am using a "standard" CP/M format of a not-so-old CP/M system (P112), and this format is supported by CP/M 3 running in simulator SIMH (the version emulating the Altair), I can create disks and transfer files from the simulator to the real Mini85.
Update: I managed to write a Floppy with a copy of CP/M 2.2 startup disk used in SIMH, corrected the warm boot code, and I filmed the boot sequence with some daylight.
Here's the new video...

Electric Bikes

Every once in a while the idea comes back... build a hybrid bicycle (pedal power/electric). I have some ideas, so I might as well write them down... Someone, somewhere, somehow having more free time, more free parts at hand and more talent could build it.
In my opinion the best way is to upgrade a recumbent tricycle, the front wheels are free-wheels and tilt slightly when you turn, they could be provided with brakes.
Auxiliary power (i.e. Electric, yes main power is pedal power) is provided to the sole traction wheel in the back. Either inside the hub, or in the chain, or even using a auxiliary wheel connected (on demand) to the main wheel.
I found some electric bikes site that also sell conversion kits and just the parts, although they do not provide much detail about the type of motor (DC series, parallel or separate excitation, AC synchronous, asynchronous/induction). I found it a bit expensive but I must agree that, at least according to the pictures, the motoring block appears well built the planetary gear is always expensive and the motor is cramped inside the hub.
Then I found some "recumbent designs" here, here, here, some electric recumbent here, a list of sites related here, an finally a "Hack a day" page.
Well the ideas have been written, now I need some time, finish all the other million projects, survive the credit crunch, wait for my bank not to go bust (or be nationalized) and pray for the best....

Creating a CP/M boot sector

In Andy Johnson-Laird's book "The Programmer's CP/M Handbook" the major steps of bringing up your own CP/M system are well explained and in this order:

1. Create your new BIOS with the appropriate device drivers in it. Assemble this so that it will execute at the top of memory (and determine the start address of the OS).
2. Create the new versions of the CCP and BDOS with all addresses inthe instructions changed so that they will be correctly located in memory just below the new BIOS. (Nowadays you can assemble this code instead of using MOVCPM)
3. Create or modify a CP/M bootstrap loader that will be loaded by the firmware that executes when you first switch on your computer.
4. Using Digital Research tools to bring the bootstrap loader, CCP, BDOS, and BIOS in the first tracks of the floppy. (I used my ROM monitor for this).

I skipped steps 1 and 2 because in a previous "incarnation" of the system I did it and I know it will be the not so dificult part. So I rewrote my Monitor disk read and write to be a little more "efficient" and used them in the bootstrap code.

After a RESET, the 8085 checks if there is a disk in drive. If so, seeks drive 0 (or A:) to track 0, and tries to read sector 1 (sector zero does not exist, only for historical reasons) into memory address 100H.

Then jumps to address 100H if it contains the byte value 0F3H, it is the code of a disable interrupts instruction (DI) in the 8080, 8085, z80, nsc800 family of microprocessors.

The bootstrap loader then reads the rest of operating system into memory (CCP,BDOS,BIOS) from the first track (sectors 2 and on). Then a jump is made to the cold boot function in the BIOS, then CP/M starts.

I used SIMH and CP/M 2.2 for assembling the code, I fell in a little trap with ASM. It recognizes the instructions SIM and RIM as labels not as instructions... I only found this by reading the assembler print out. I had to use a DB 30H for SIM and a DB 20H for RIM, then it worked ok.

The Boot Sector Code is posted here.

More pseudo-DMA circuits

In my search for new alternatives I found two more schematics in a very good article. The article titled "Floppy Disk Data transfer techniques" by T. Marshall and J. Attikiouzel and was published in IEEE Micro in December 1983. The article is a bit Z80 centric but easily adaptable to other microprocessors.

The first technique is using a edge triggered interrupt and the HALT instruction (NMI in the Z80 or RST7.5 or TRAP in the 8085), the interrupt routine is void but although in the z80 it is automatically cleared on interrupt entry, on the 8085 two extra instructions must be used in the ISR.

The second technique is the WS (wait state) insertion while waiting for the floppy to get the data. This is a similar technique to the one I'm using in the mini85, the schema proposed has more control options as sensing the interrupt call and determine an error, conditional enabling of WS insertion.

On the Z80 both these methods allow and profit in terms of timing by executing the INI instruction, one instruction fetch with 3 operations executed (IN (C),INC HL,DCR B).

Hopefully I will use a combination of both methods, WS insertion for data reads and writes and halting the processor for seek/recall operations.