It turned out it could not be done, at least as far as I tried. The data separator FDC 9216 cannot read 500kbps without an 8MHz input, from the datasheet it is impossible to get that rate without an 8MHz clock. The WRCLK divisor could work but I would need to change the divisor ratio, but the 765 didn't seem to like the 4MHz clock at all as it was unable to read any sector, even increasing the byte loop and changing the specify parameters.
Finally I have a reached the final hardware configuration for this project. My current IC count is only 16!
- 8085AH-2 @ 4MHz (8MHz crystal)
- 74HC573 (address latch)
- 27C256 (EPROM emulator 32K bytes)
- 62256ALP-10 (system RAM 32K bytes)
- MAX232 (serial interface)
- 7400 (used as 4 inverters...!!)
- 74HC139 (address and IO decoder)
- 74LS08 (address decoder, only 2 ports used)
- 74HC259 (addressable latch, serial port, memory flip)
- LM555 (motor on delay)
- 74HC161 (WRCLK divider)
- UPD765 (Floppy Disc Controller IC)
- 74HC14 (FDC Interface to the drive)
- FDC9216 (Data separator for 3.5 HD drive)
- 74LS32 (FDC Interface to the drive)
- 74LS240 (FDC Interface to the drive)
There might be some more optimizing to do, I'm going to try and use gEDA gschem to draw the schematic and I'll post them as soon as their finished.