It is amazing how the ideas flow once you put the schematic on paper... or screen... I wrote a list of possible improvements for the next circuit iteration.
- try (again) changing the FDC765 clock circuit down to 4MHz;
- change the FDC interrupt to RST7.5;
- change CRT_RXD input to RST6.5;
- change RDR input to RST5.5 (instead of SID);
- change PUN output to one of the 74HC259;
- do a system request input in INTR or TRAP inputs;
- do the LPT interface (with STROBE and PERROR);
- upgrade the system to full 64k bytes. (play Zork!)
- decide what to do with SID input and SOD outputs ?
- lights for RDY, INTA, floppy, etc..
- add the switching power supply and the MOTOR ON one-shot to the schematics.
- disable CRT/RDR interrupts while on FDC read/write cycle (blocks the system);
- put the processor in HALT while waiting for a character (save power);
- implement the RDR and PUN functions;
- implement the LST function;
- during a warm boot, read the operating system all at once instead of sector by sector (faster);
- change interrupts to follow the hardware changes above;
- either put most of the BIOS in ROM (32K) or in upper RAM (64K).
The problem with the 64K expansion is that it would use a second RAM IC, that takes up valuable breadboard space (as I have a three breadboard limit), plus probability of failing due to wiring. I think I can still make some more optimizations on the IC's used.
1 month ago