Well, after some tests I'm confident that my 8085 DRAM interface is working properly!
My first test executed from EPROM and at the end of every instruction fetch cycle does a CAS-before-RAS (C-B-R) refresh.
The second test wrote a value to the DRAM and latter read it back, still executing from EPROM, a C-B-R refresh was done at every instruction fetch.
The third test I tried writing once and read many times, and if at some point the values differed halt the processor (this would terminate refreshing). It worked, no Halts!
On the fourth test I decided to go a bit more ambitious, not only I initialized the stack to the DRAM I also placed a RET instruction in the DRAM. The program in the EPROM would then call the RET instruction and return to EPROM. This would trigger an instruction fetch in the DRAM and respective hidden refresh.
Here's a picture of the execution of the RET instruction and respective hidden refresh, top signal is RAS bottom is CAS.
Done, my "home-made"dynamic ram refresh circuit works, now I'll have to try with other microprocessors...
1 month ago